The chip is implemented in a m CMOS process and occupies a die area of around 5 mm. Operating from a V power supply, the chip achieves an energy efficiency of $ 0.47$ pJ/MAC.
In this paper, we describe a compact low-power, high performance hardware
implementation of the extreme learning machine (ELM) for machine learning
applications. Mismatch in current mirrors are used to perform the vector-matrix
multiplication that forms the first stage of this classifier and is the most
computationally intensive. Both regression and classification (on UCI data
sets) are demonstrated and a design space trade-off between speed, power and
accuracy is explored. Our results indicate that for a wide set of problems,
in the range of mV gives optimal results. An input weight
matrix rotation method to extend the input dimension and hidden layer size
beyond the physical limits imposed by the chip is also described. This allows
us to overcome a major limit imposed on most hardware machine learners. The
chip is implemented in a m CMOS process and occupies a die area of
around 5 mm 5 mm. Operating from a V power supply, it achieves an
energy efficiency of pJ/MAC at a classification rate of kHz.